EDN

Clock randomization automated methodology to validate SoC designs

The demand for new and upgraded features is increasing day by day in modern semiconductors. This may include multiple power domains to support low power and full power modes and multiple clock domains ...
EDN

Improving fault coverage for random-pattern-resistant designs

Designs with LogicBIST exhibit random pattern resistance because of the random nature of LBIST vectors, thus leading to low fault coverage. To handle this, we insert test points with the help of ...
Design-Reuse

Lockdown! Random Numbers Secure Network SoC Designs

Editor's note: To view a PDF version of this article, click here. The demand for networking equipment that incorporates virtual private networking (VPN) functionality is growing, fueled by companies' ...
Nature

Embedded Dynamic Random Access Memory Design

Embedded Dynamic Random Access Memory (eDRAM) design is rapidly evolving to meet the escalating performance and energy efficiency demands of contemporary processors. This technology has emerged as a ...