Electronic Design

Optimal Jitter Attenuation Starts With The Proper PLL Bandwidth

Clock signals provide reference timing to every integrated circuit and electrical system. Consumer applications typically use simple quartz crystals for reference clock generation. Other applications, ...
Design-Reuse

Ultra Low Jitter Wide Band LC PLL

The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for current and next generation SerDes transceivers. Not only must they handle multiple ...
Electronic Design

Select The Right PLL-based Oscillator For Your Timing Application

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional ...
EDN

Phase coordination to achieve more ideal PLL/DLL

A new method of phase coordinating to enhance PLL/DLL design is introduced herein. This method, known as Ultimate Phase Tracking, eliminates jitter peaking thus enabling applications like Digital FM, ...
Design-Reuse

Is there a "one-size fits all" SOC PLL?

A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more ...
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
EDN

Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 1 of 2)

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...