Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief ...

Synopsys, Inc. (NASDAQ: SNPS) today launched Ansys 2026 R1, delivering the first wave of integrated Synopsys-Ansys ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...

As the cost of chip turns has grown from thousands to millions of dollars, missed design bugs are unacceptable Chip design verification used to be straightforward, if not always easy. Verification ...

New design, verification and simulation solutions to re-engineer AI-powered product innovation at Synopsys Converge 2026.