Nature

Low-Density Parity-Check Decoder Architectures and Algorithms

Low-Density Parity-Check (LDPC) decoder designs have undergone significant evolution, driven by the need for high-throughput, low-complexity and energy-efficient ...
Design-Reuse

Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding

This paper describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other ...
Design-Reuse

Stochastic Computation applied to the design of Error Correcting Decoders

We describe the application of stochastic computation to a family of error-correcting decoders. We have applied this technology to the Low Density Parity Check (LDPC ...